Field of the Invention
This invention relates to memory arrays and, in particular to formation of self-formed contacts and self-aligned source lines in memory arrays.
Description of Related Art
Arrays comprising memory cells are well known in the art. Illustrative memory cells include electrically-programmable read only memories (EPROMs), flash EPROMs, electrically-erasable programmable read only memories (EEPROMs), and dynamic random access memories (DRAMs). In general, the smaller the memory cell size the smaller the integrated circuit die or chip containing a given number of memory cells, and therefore the higher the yield of useful semiconductor dice in the manufacturing process. Moreover, because a smaller memory cell size results in a smaller integrated circuit die for a given size memory cell array, more semiconductor dice can be obtained from a given size wafer, thereby lowering the manufacturing cost per die. As shown in FIG. 1, EPROM density, for example, doubles on the average every 1.8 years. The density of flash EPROMS doubles at even a faster rate. However, the size of the associated EPROM cells (in area dimensions) has not decreased at the same rate and, in fact, has halved approximately every 3.5 years, as illustrated graphically by curve 200 in FIG. 2. Thus, die size is dramatically increasing. The actual memory cell size (curve 200) remains larger than the theoretical minimum cell size (curve 201) because of non-self-aligned design rules currently limiting size reduction of the cell. Therefore, a need arises to reduce memory cell size to more nearly approximate the minimum theoretical cell size (i.e., lithographic limit), thereby reducing die size.